In this paper, we report on the design of a class of analog filters based on the cascode circuit structure surrounded by four impedances. The proposed topology is systematically investigated using two-port network techniques and symbolic math CAD tools. A total of 106 second-order filter circuits can be obtained from this class including 9 low-pass filters, 6 high-pass filters, 73 bandpass filters, 6 band-stop filters, and 12 gain equalizer/all-pass filters. Post-layout simulations in 65-nm CMOS technology of selected members of this family of filters are provided and prove its correct

A structure suitable for implementing power-law low-pass and high-pass filter transfer functions is presented in this work. Through the utilization of a field-programmable analog array device, full programmability of the characteristics of the intermediate stages, as is required for realizing the rational integer-order transfer function that approximates the corresponding power-law function, was achieved, making the structure versatile. In addition, a comparison between power-law and fractional-order filters regarding the effect of the non-integer order was performed. The presented design

The success of fractional-order fractance (FOF) as a modeling tool in (photo)bio(electro)chemical systems can be readily gauged by the large body of research work that has been conducted over the past few years in terms of materials fabrication, building integer-order emulators of their behavior, as well as applications in filter design, controller design, modeling of energy storage devices and biomaterials. The impedance of FOF has the general form Zα(s)=kαsα where kα and α are real constant and s=jω is the complex Laplace number. In this work, we investigate the possibility of decoupling the

The main goal of this work is to exploit different tools in order to approximate a general double exponent fractional-order transfer function. Through the appropriate selection of the two fractional orders of this function, different types of filters can be derived. The investigated approximation tools are either curve fitting based tools or the Padé approximation tool, and the derived approximated transfer functions in all cases have the form of rational integer-order polynomials, which can be easily realized electronically. © 2020, Springer Science+Business Media, LLC, part of Springer

This paper proposes an efficient encryption technique based on Dynamic and Secure Substitution Box (DS2B) design suitable for IoT and resource-constrained platforms. The DS2B has the advantages of simple structure and good encryption performance. A different number of strong S-boxes could be generated with minor variations in the DS2B parameters. Performance analyses of the DS2B, including differential/linear cryptanalysis, bijective, nonlinearity, strict avalanche criterion (SAC), and bit independence criterion (BIC) have been presented where high nonlinearity , and low differential

This paper presents a generalization, attractor control and multi-scroll generation method for fractional-order chaotic systems through rotation transformation. A novel synchronization-dependent colored image encryption and secure communication scheme is also proposed. The systems with dynamic rotation angle fit successfully in a generalized dynamic switched synchronization scheme. Dynamic control switches specify whether the system acts as a master or slave. Dynamic scaling factors determine whether the master is a single system or a combination of two or more systems. Simulation results

In this letter, a third-order wideband voltage-mode all-pass filter (APF) is proposed for application as a true time delay (TTD) cell. The advantages of designing a single-stage higher order filter over cascading several lower order stages are illustrated. The proposed APF circuit is based on a single metal-oxide-semiconductor (MOS) transistor and is canonical because it requires one resistor, one inductor, and two capacitors. To the best of the authors' knowledge, this is the first single-transistor third-order APF circuit to be reported in the literature. The operation of the proposed APF is

A novel scheme suitable for the emulation of fractional-order capacitors and inductors of any order less than 2 is presented in this work. Classically, fractional-order impedances are characterized in the frequency domain by a fractional-order Laplacian of the form s± α with an order 0 < α< 1. The ideal inductor and capacitor correspond, respectively, to setting α= ± 1. In the range 1 < α< 2 , fractional-order impedances can still be obtained before turning into a Frequency- Dependent Negative Resistor (FDNR) at α= ± 2. Here, we propose an electronically tunable fractional-order impedance

In this study we quantify and interpret the inherent memory in fractional-order capacitors when subjected to constant current charging/discharging waveforms. This is done via a finite difference approximation of the fractional order rate equation I(t) = Cαdαv(t)/dtα (0 le; α ≤ 1) relating current to voltage in these devices. It is found that as the fractional exponent α decreases, the weight of the voltage memory trace that results from the contribution of past voltage activity increases, and thus the measured response of the device at any time is increasingly correlated to its past. Ideal

In this paper, a CMOS wide-band low-power second-order voltage-mode allpass filter design is proposed as a true time delay element. The proposed allpass filter core design consists of a single transistor, three resistors, one capacitor and one inductor. As a time delay element, the proposed circuit exhibits a group delay of 34 ps within a bandwidth of 8 GHz while consuming only 926 μW from a 1-V supply voltage. The proposed filter was designed in 65-nm CMOS technology and verified through post-layout simulation results. © 2019 IEEE.