Timing verification is an essential process in nanometer design. Therefore, static timing analysis (STA) is currently the main aspect of performance verification. Traditional STA is based on lookup tables with input slew and output load capacitance. It is becoming insufficient to accurately characterize many significant aspects of the conventional cell delays models, such as: the process variations, nonlinear waveforms, nonlinear loads, and multiple inputs switching (MIS). Therefore, the current trend in modern designs is to use current source based models (CSM), which model MOSFETs as a

This paper presents a new technique to reduce the conversion time, hence improve the throughput, of the two-stage Time to Digital Converter (TDC) architecture. An oscillator based TDC is used in the first and second stages. The time residue from the first stage is generated directly after the stop signal is asserted and saved in the form of phase-shift between two oscillating signals. A throughput of 400 MS/s, a DNL of 0.38, and an INL of 0.36 are achieved. © 2013 IEEE.

This paper introduces the modified single input Op-Amps memristor based oscillator. The oscillator is realized with ideal, LM741 and current feedback (AD844) Op-Amps where memristors replace resistors. The effect of memristor on the oscillation frequency and the oscillation condition that are totally independent is studied. This helped in studying the whole operation regime of the memristor. The effect of initial conditions on the circuit behavior is discussed. The dynamic poles of the oscillator after resistors replacement are illustrated. Sustained oscillation is obtained and simulated

This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput

An ultra low power wake-up receiver for Wireless Sensor Network (WSN) applications is presented. The proposed wake-up receiver is composed of two stages. The first stage is a low-power low-sensitivity stage that acts as a 'sentinel' and continuously monitors the channel, while the second stage is a conventional low-power wake-up receiver. The 2.44GHz two-stage receiver has a sensitivity of -72dBm when the transmitted signal power is 0dBm. The power consumed during sleep mode is 2.5μWatts and 41μWatts in the wake-up receiver active mode with a 0.5V supply voltage. The power consumption is

Mem-element based synaptic bridge is very promising topic due to its learning capability where the synaptic bridge can be build using either memristors or memcapacitors. In this paper, the detailed mathematical analysis of memcapacitor bridge circuit is introduced. This mathematical analysis is build when a current input signal is applied to excite the bridge. Closed form expressions for the required pulse width; synaptic weight; and conditions for positive, negative and zero synaptic weight are derived. The obtained expressions are verified using SPICE simulations showing very good matching.

Current-voltage analysis using different optical band pass filters has been performed on Cu2ZnSnSe4 and Cu2ZnSn(S,Se) 4 thin-film solar cells. When using red or orange light (i.e. wavelengths above 600 nm), a distortion appears in the I-V curve of the Cu 2ZnSnSe4 solar cell, indicating an additional potential barrier to the current flow in the device for these conditions of illumination. This barrier is reduced when using a Cu2ZnSn(S,Se)4 absorber. Numerical simulations demonstrate that the barrier visible under red light could be explained by a positive conduction band offset at the front

This paper introduces two mathematical models of meminductor based on a simple symmetrical double-loop equation with their generic formulas and analysis. Moreover, new circuits based on CCII are developed for emulating the behavior of the current-controlled and voltage-controlled models. The proposed circuits are realized without using a memristor unlike the previous emulators. Finally, the proposed emulators are verified using PSPICE simulations. © 2014 IEEE.

This paper presents a study of fractional order oscillators based on current feedback operational amplifiers (CFOA). Two general cases have been discussed for the oscillation frequency and condition with the use of two fractional order elements of different orders. Design procedure for the two general cases is illustrated with numerical discussions. Circuit simulations for some special cases are presented to validate the theoretical findings. The simulations have been done using Ad844 commercial CFOA model © 2014 IEEE.

Abstract Pinched hysteresis is considered to be a signature of the existence of memristance. However, here we report on a model that exhibits pinched hysteresis yet it may represent a nonlinear inductor or a nonlinear capacitor (both with quadratic nonlinearity) or a derivative-controlled nonlinear resistor/transconductor. Further, the lobe area of the pinched hysteresis loop in these devices has inverse-memristor characteristics; i.e. it is observed to widen rather than decline with increased operating frequency. Experimental results are provided to validate the model. © 2015 Elsevier Ltd.